View ADXL375BCCZ-RL7_6932345.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3 - axis, 200 g digital accelerometer data sheet adxl375 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliab le. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implicati on or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features l ow power: as low as 3 5 a in measurement mode and 0.1 a in standby mode at v s = 2.5 v power consumption scales automatically with bandwidth embedded, 32 - level fifo buffe r minimizes processor load b andwidth of up to 1 khz bandwidth selectable via serial command shock event detection activity/inactivity monitoring supply voltage range: 2.0 v to 3.6 v i/o voltage range: 1.7 v to v s spi (3 - or 4 - wire) and i 2 c digital interfaces wide temperature range: ?40c to +85c 10,000 g shock survival pb free/rohs compliant small and thin: 3 mm 5 mm 1 mm lga package applications concussion and h ead t rauma d etection high force event detection general description the adxl375 is a small, thin, 3 - axis accelerometer that provides low power consumption and high resolution measurement up to 200 g . the digital output data is formatted as 16 - bit, twos complement data and is accessible through a spi (3 - or 4 - wire) or i 2 c digital interface. an integrated memory management system with a 32 - level first in, first out (fifo) buffer can be used to store data to minimize host processor activity and lower ov erall system power consumption. low po wer modes enable intelligent motion - based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. the adxl375 is supplied in a small, thin, 3 mm 5 mm 1 mm, 14 - lead lga . functional block dia gram 3-axis sensor sense electronics digi t al fi l ter adxl375 power management contro l and interrupt logic seria l i/o int1 v s v dd i/o int2 sda/sdi/sdio sdo/a l t address scl/sclk gnd adc 32-leve l fifo cs 1 1669-001 figure 1.
adxl375 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applic ations ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revisi on history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 soldering profile ........................................................................... 5 pin configuratio n and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 power sequencing ...................................................................... 10 current consumption and output data rate ........................ 10 power saving modes .................................................................. 11 fifo buffer ................................................................................. 11 self - te st ........................................................................................ 12 interrupts ......................................................................................... 13 enabling and disabling interrupts ........................................... 13 clearing interrupts ..................................................................... 13 bits in the interrupt registers ................................................... 13 serial communications ................................................................. 15 spi mode ..................................................................................... 15 i 2 c mode ...................................................................................... 18 register map ................................................................................... 20 register descriptions ................................................................. 21 applications information .............................................................. 26 power supply decoupling ......................................................... 26 mechanical considerations for mounting .............................. 26 shock detec tion ......................................................................... 26 threshold detection and bandwidth ...................................... 27 link mode ................................................................................... 27 sleep mode vs. low power mode ............................................. 28 offset calibration ....................................................................... 28 data formatting at output data rates of 3200 hz and 1600 hz ................................................................................ 28 using self - te st ............................................................................ 29 axes of acceleration sensitivity ............................................... 30 layout and design recomm endations ................................... 31 package information .................................................................. 31 outline dimensions ....................................................................... 32 orderi ng guide .......................................................................... 32 revision history 8 /13 revision 0 : initial version
data sheet adxl375 rev. 0 | page 3 of 32 specifications t a = 25c, v s = 2.5 v, v dd i/o = 2.5 v, acceleration = 0 g , c s = 10 f tantalum, c i/o = 0.1 f, output data rate ( odr) = 800 hz, unless other wise noted. table 1 . parameter test conditions /comments min typ 1 max unit sensor input each axis measurement range 2 180 200 g nonlinearity percentage of full scale 0. 2 5 % cross - axis sensitivity 3 2.5 % sensitivit y each axis sensitivity at x out , y out , z out 2 , 4 odr 800 hz 18.4 20.5 22.6 lsb/ g scale factor at x out , y out , z out 2 , 4 odr 800 hz 44 49 54 m g /lsb sensitivity change due to temperature 0.02 %/c 0 g offset each axis 0 g output for x out , y out , z out ? 6000 400 + 6000 m g 0 g offset vs. temperature 10 m g /c noise x -, y - , and z - axes 5 m g / hz output data rate and ban dwidth 5 user selectable output data rate (odr ) 4 , 6 0.1 3200 hz self - test 7 output change in z - axis 6.4 g power supply operating voltage range (v s ) 2.0 2.5 3.6 v interface voltage range (v dd i/o ) 1.7 1.8 v s v supply current measurement mode odr 100 hz 145 a odr 3 hz 35 a standby mode 0.1 a turn - on and wake - up time 8 odr = 3200 hz 1.4 ms temperature operating temperature range ?40 +85 c weight device weight 30 mg 1 t ypical specification s are f or a t least 68% of the population of parts and are based on the worst case of mean 1 distribution, except for sensitivity, which represents the target value. 2 m inimum and maximum specifications represent the worst case of mean 3 distribution and are n ot guaranteed in production. 3 cross - axis sensitivity is defined as coupling between any two axes. 4 the output format for the 1600 hz and 3200 hz output data rates is different from the output format for the other output data rates. for more information, see the data formatting at output data rates of 3200 hz and 1600 hz section. 5 bandwidth is the ?3 db frequency and is half the output data rate: bandwidth = odr/2. 6 output data rates < 6.25 hz exhibit additional offset shift wit h increased temperature. 7 self - test change is defined as the output ( g ) when the self_test bit = 1 (data_format register, address 0x31) minus the output ( g ) when the self_test bit = 0. due to device filtering, the output reaches its final value after 4 when enabling or disabling self - test, where = 1/(data rate). f o r the self - test to operate correctly, t he part must be in normal power operation (low_power bit = 0 in the bw_rate register, address 0x2c). 8 turn - on and wake - up times are determined by th e user - defined bandwidth. at a 100 hz data rate, the turn - on and wake - up times are each approximately 11.1 ms. for other data rates, the turn - on and wake - up times are each approximately + 1.1 ms , where = 1/(data rate).
adxl375 data sheet rev. 0 | page 4 of 32 absolute maximum rat ings table 2 . parameter rating acceleration , any axis unpowered 10,000 g powered 10,000 g v s ?0.3 v to +3.9 v v dd i/o ?0.3 v to +3.9 v digital pins ?0.3 v to v dd i/o + 0.3 v or 3.9 v, whichever is less output short - circuit duration (any pin to ground) indefinite temperature range powered ?40c to +105c storage ?40c to +105c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the dev ice at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specif ied for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . package characteristics package type ja jc unit 14- terminal lga 150 85 c/w esd caution
data sheet adxl375 rev. 0 | page 5 of 32 soldering profile figure 2 and table 4 provide information about the recommended soldering profile. t p t l t 25c t o peak t s prehe a t critica l zone t l t o t p temper a ture time ramp-down ramp-u p t smin t smax t p t l 1 1669- 015 figure 2 . recommended soldering profile table 4 . recommended soldering profil e limits 1, 2 profile feature sn63/pb37 pb - free average ramp rate (t l to t p ) 3c/sec maximum 3c/sec maximum preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time from t smin to t smax (t s ) 60 sec to 120 sec 60 sec to 180 sec ramp - up rate ( t smax to t l ) 3c/sec maximum 3c/sec maximum liquidous temperature (t l ) 183c 217c time maintained above t l (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240c +0c/?5c 26 0c +0c/?5c time within 5c of actual t p (t p ) 10 sec to 30 sec 20 sec to 40 sec ramp - down rate 6c/sec maximum 6c/sec maximum time 25c (t25c) to peak temperature 6 minutes maximum 8 minutes maximum 1 based on jedec standard j - std - 0 20d.1. 2 for best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder pa ste used.
adxl375 data sheet rev. 0 | page 6 of 32 pin configuration an d function descripti ons 1 1669-002 cs sda/sdi/sdio sdo/a l t address rese r ved nc notes 1. nc = not internal l y connected. int2 int1 v dd i/o gnd rese r ved gnd gnd v s 13 12 1 1 10 9 8 1 2 3 4 +x + y +z 5 6 14 7 scl/sclk adxl375 t o p view (not to scale) figure 3 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 v dd i/o digital interface supply voltage. 2 gnd ground. this pin must be connected to ground. 3 reserved re served. this pin must be connected to v s or left open. 4 gnd ground. this pin must be connected to ground. 5 gnd ground. this pin must be connected to ground. 6 v s supply voltage. 7 cs chip select. 8 int1 interrupt 1 output. 9 i nt2 interrupt 2 output. 10 nc not internally connected. 11 reserved reserved. this pin must be connected to ground or left open. 12 sdo/alt address spi 4 - wire serial data output ( sdo )/ i 2 c alternate address select (alt address). 13 sda/sdi/sdio i 2 c seri al data (sda) / spi 4 - wire serial data input (sdi) / spi 3 - wire serial data input and output (sdio). 14 scl/sclk i 2 c serial communications clock (scl)/ spi serial communications clock (sclk).
data sheet adxl375 rev. 0 | page 7 of 32 typical performance characteristics 0 ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 5 10 15 20 25 percent of population (%) offset ( g) 11669-200 figure 4. x - axis zero g offset at 25c, v s = 2.5 v 0 ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 5 10 15 20 25 percent of population (%) offset ( g) 11669-201 figure 5. y - axis zero g offset at 25c, v s = 2.5 v ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 percent of population (%) offset ( g ) 11669-202 0 2 4 6 8 10 12 14 16 figure 6. z - axis zero g offset at 25c, v s = 2.5 v ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 offset drift ( g ) temper a ture (c) 11669-203 figure 7. x - axis offset drift, 15 parts soldered to pcb, v s = 2.5 v ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 offset drift ( g ) temper a ture (c) 11669-204 figure 8. y - axis offset drift, 15 parts soldered to pcb, v s = 2.5 v ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 offset drift ( g) temper a ture (c) 11669-205 figure 9. z - axis offset drift, 15 parts soldered to pcb, v s = 2.5 v
adxl375 data sheet rev. 0 | page 8 of 32 0 5 10 15 20 25 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 percent of popul a tion (%) sensitivit y (lsb/ g ) 11669-206 figure 10 . x - axis sensitivity at 25c, v s = 2.5 v 0 5 10 15 20 25 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 percent of popul a tion (%) sensitivit y (lsb/ g) 11669-207 figure 11 . y - axis sensitivity at 25c, v s = 2.5 v 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0 percent of popul a tion (%) sensitivit y (lsb/ g) 11669-208 0 2 4 6 8 10 12 14 16 figure 12 . z - axis sensitivity at 25c, v s = 2.5 v 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 sensitivit y (lsb/ g) temper a ture (c) 11669-209 figure 13 . x - axis sensitivity vs. temperature, 16 parts soldered to pcb, v s = 2.5 v 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 sensitivit y (lsb/ g ) temper a ture (c) 11669-210 figure 14 . y - axis sensitivity vs. temperature, 16 parts soldered to pcb, v s = 2.5 v 18.0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 22.5 23.0 ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 sensitivit y (lsb/ g ) temper a ture (c) 11669-211 figure 15 . z - axis sensitivit y vs. temperature, 16 parts soldered to pcb, v s = 2.5 v
data sheet adxl375 rev. 0 | page 9 of 32 0 5 10 15 20 25 80 85 90 95 100 105 1 10 1 15 120 125 130 135 140 145 150 155 160 165 170 175 180 percent of popul a tion (%) self-test response (lsb) 11669-212 figure 16 . z - axis self - test response at 25c, v s = 2.5 v 0 5 10 15 20 25 100 1 10 120 130 140 150 160 170 180 190 200 current consumption (a) percent of popul a tion (%) 11669-213 figure 17 . current consumption at 25c, 100 hz output data rate, v s = 2.5 v 0 20 40 60 80 100 120 140 160 1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200 output d at a r a te (hz) current consumption (a) 11669-214 figu re 18 . current consumption vs. output data rate at 25c , 10 parts soldered to pcb, v s = 2.5 v 0 50 100 150 200 2.0 2.4 2.8 3.2 3.6 supp l y vo lt age (v) supp l y current (a) 11669-215 figure 19 . supply current vs. supply voltage (v s ) at 25c 0 50 100 150 200 0 50 100 150 200 output ( g) reference acceler a tion ( g) y -axis, du t 1 y -axis, du t 2 x -axis, du t 1 x -axis, du t 2 z -axis, du t 1 z -axis, du t 2 11669-216 figure 20 . output li nearity over the dynamic range 0 0.2 0.4 0.6 0.8 1.0 1.2 10 100 1000 normalized sensitivit y frequenc y (hz) x-axis y -axis z -axis 11669-217 figure 21 . frequency response
adxl375 data sheet rev. 0 | page 10 of 32 theory of operation the adxl375 is a complete 3 - axis acceler ation measurement system with a measurem ent range of 2 00 g . it measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity. the sensor is a polysilicon surface - micromachined structure built on top of a silicon wafer. polysilicon springs suspend the structure over the surface of the wafer and provide resistance against forc es due to applied acceleration. deflection of the structure is measured using differential capac - itors that consist of independent fixed plates and plates attached to the moving ma ss. acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. phase sensitive demodulation is used to determine the magnitude and polarity of the accelerati on. power sequencing power can be applied to v s or v dd i/o in any sequence without damaging the adxl375 . table 7 provides a description of all the power modes . the interface voltage level is set using the interface supply voltage, v dd i/o , which must be present to ensure that the adxl375 does not create a conflict on the communi - cation bus. for s ingle - supply operation, v dd i/o can be the same as the main supply, v s . in a dual - supply application, however, v dd i/o can differ from v s to accommodate the desired interface voltage , as long as v s is greater than or equal to v dd i/o . after v s is applied, the device enters standby mode . in standby mode , power consumption is minimized ; the device waits for v dd i/o to be applied and for the command to enter measurement mode . this command can be initiated by setting the measure bit (bit d3) in the pow er_ctl re gister (address 0x2d). w h en the device is in standby mode, any register can be written to or read from. it is recommended that the device be configured in standby mode before enabling measurement mode. clearing the measure bit returns the device to standb y mode. current consumption and outp ut data rate the adxl375 automatically modulates its current consumption in proportion to its output data rate (see table 6 ). the device bandwidth and output data rate are specified using the rate bits (bit s[d3:d0] ) in the bw_rate register (address 0x2c) . table 6 . typical current consumption vs. data rate (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) rate bits output data rate (hz) bandwidth (hz) i dd (a) 1111 3200 1600 145 1110 1600 800 90 1101 800 400 140 1100 400 200 140 1011 200 100 140 1010 100 50 140 1001 50 25 90 1000 25 12.5 60 0111 12.5 6.25 50 0110 6.25 3.13 40 0101 3.13 1.56 35 0100 1.56 0.78 35 0011 0.78 0.39 35 0010 0.39 0.20 35 0001 0.20 0.10 35 0000 0.10 0.05 35 table 7 . power modes power mode v s v dd i/o description power off off off the device is completely off, but it is still possible for the device to create a conflict on the communication bus. bus disabled on off the device is on in standby mode, but communication is unavailable and the device can create a conf lict on the communication bus. m inimize t he duration of the bus d isabled state during power - up to prevent a conflict on the communication bus . bus enabled off on no functions are available, but the device does not create a conflict on the communication bus. standby or measurement on on at power - up, the device is in standby mode, a waiting a command to enter measurement mode, and all sensor functions are off. after the device is instructed to enter measurement mode, all sensor functions are available.
data sheet adxl375 rev. 0 | page 11 of 32 power saving modes low power mode a low power mode is available for addition al power savings . in low power mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 hz to 400 hz data rate range at the expense of slightly greater noise. to enter low power mode, set the low_power bit (bit d 4) in the bw_rate register (address 0x2c). table 8 shows the current consumption in low power mode for output data rates where there is an adv antage to using low power mode. table 8 . typical current consumpt ion vs. data rate, low power mode ( t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v ) rate bits output data rate (hz) bandwidth (hz) i dd (a) 1100 400 200 9 0 1011 200 100 6 0 1010 100 50 5 0 1001 50 25 45 1000 25 12.5 4 0 0111 12.5 6.25 3 5 f or data rate s not sho wn in table 8 , the u se of low power mode does not provide any advantage over normal power mode. there - fore, it is recommended that low power mode be used only for the data rates shown in table 8 . autos leep mode additional power can be saved if the adxl375 automatically switches to sleep mode during periods of inactivity. to enable t he auto sleep mode feature, 1. s et t he thresh_inact register (address 0x25) and the time_inact register (address 0x26) to value s that signify inactivity . t he appropriate value s depend on the application . 2. s et the auto_sleep bit (bit d4) and the link bit (bit d5) in the pow er_ctl register (ad dress 0x2d). current consumption at the sub - 12.5 hz data rates that are used in auto sleep mode is typically 35 a for v s = 2.5 v. for information about the advantages of using low power mode vs. autosleep mode, see the sleep mode vs . low power mode section. standby mode for even lower power operation, standby mode can be used. in standby mode, current consumption is reduced to 0.1 a (typical). in this mode, no measurements are made , but the contents of the fifo bu ffer are preserved . to enter s tandby mode , clear the measure bit (bit d3) in the pow er_ctl register (address 0x2d). fifo buffer the adxl375 contains patented technology for an embedded memory management system with a 32- level fifo buffer that can be used to minimize host processor burden. this buffer has four modes: bypass, fifo, stream, and trigger. each mode can be selected by setting the fifo_mode bits (bits[d7:d6]) in the fifo_ctl register ( address 0x38 ; see table 9 ). table 9 . fifo modes ( fifo_ctl register, address 0x38) setting fifo mode d 7 d 6 description 0 0 bypass fifo buffer is bypassed. 0 1 fifo fifo buffer collects up to 32 sampl es and then stops collecting data, collecting new data only when the buffer is not full. 1 0 stream fifo buffer holds the last 32 samples . when the buffer is full, the oldest data is overwritten with newer data. 1 1 trigger fifo buffer holds the last samp les before the trigger event and continues to collect data until full. new data is collected only when the buffer is not full. for an in - depth description of the fifo buffer and fifo modes, see the an - 1025 application note , utilization of the first in, first out (fifo) buffer in analog devices, inc., digital accelerometers . bypass mode in bypass mode, the fifo buffer is not operational and, there - fore, remains empty. fifo mode in fifo mode, dat a from measurements of the x - , y - , and z - axes is stored in the fifo buffer . when the number of samples in the fifo buffer equals the level specified by the samples bits of the fifo_ctl register (address 0x38), the watermark interrupt is set (see the watermark bit section) . the fifo buffer continues to accumulat e samples until it is full (32 samples from measure - ments of the x - , y - , and z - axes) and then stops collect ing data. after the fifo buffer stops collecting data, the device c ontinues to operate; therefore, features such as shock detection can be used after the fifo buffer is full. the watermark interrupt bit remains set until the number of samples in the fifo buffer is less than the value stored in the samples bits of the fifo _ctl register. stream mode in stream mode, data from measurements of the x - , y - , and z - axes is stored in the fifo buffer . when the number of samples in the fifo buffer equals the level specified by the samples bits of the fifo_ctl register (address 0x38), the watermark interrupt is set (see the watermark bit section) . the fifo buffer continues to accu mulate samples ; the buffer stores the latest 32 samples from measurements of the x - , y - , and z - axes, discarding older data as new dat a arrives. the watermark interrupt bit remains set until the number of samples in the fifo buffer is less than the value stored in the samples bits of the fifo_ctl register.
adxl375 data sheet rev. 0 | page 12 of 32 trigger mode in trigger mode, the fifo buffer accumulates samples, stor ing the lat est 32 samples from measurements of the x - , y - , and z - axes. after a trigger event occurs , an interrupt is sent to the int1 or int2 pin (determined by the trigger bit in the fifo_ctl register) , and the fifo_trig bit (bit d7) is set in the fifo_status regist er (address 0 x39) . t he fifo buffer keeps the last n samples (n is the value specified by the samples bits in the fifo_ctl register) and then operates in fifo mode, collecting new samples only when the fifo buffer is not full. a delay of at least 5 s must elapse between the occur - rence of the trigger event and the start of data read back from the fifo buffer to allow the buffer to discard an d retain the necessary samples. additional trigger events cannot be recognized until the part is reset to trigger mode. to reset the part to trigger mode, 1. if desired, read data from the fifo buffer (see the retrieving data from the fifo buffer section) . before resetting the part to trigger mode, read back the fifo data; p lacing th e device into bypass mode clears the fifo buffer. 2. configure the device for bypass mode by setting bits[d7:d6] at address 0x38 to 00 . 3. configure the device for trigger mode by setting bits[d7:d6] at address 0x38 to 11 . retrieving data from the fifo buffer wh en the fifo buffer operates in fifo, stream, or trigger mode, fifo data can be read from the data registers (address 0x32 to address 0x37). each time data is read from the fifo buffer , the oldest x - , y - , and z - ax i s data is mov ed into the datax, datay , and dataz registers. if a single - byte read operation is performed, the remaining bytes of data for the current fifo sample are lost. therefore, data for all axes of interest must be read in a burst (multiple - byte) read operation. to ensure that the fifo buffer is empty (that is, all new data has moved into the data registers), an interval of at least 5 s must elapse between the end of the read back from the data registers and the start of a new read of the data registers or the fifo_status register (address 0x3 9). the end of a read operation from the data register s is signified by the transition from register 0x37 to register 0x38 or by the cs pin going high. when spi operation is enabled at a frequency of 1.6 mhz or lower , the register add ressing portion of the transmission provides a sufficient delay to ensure that the fifo buffer has completely emptie d. when spi operation is enabled at a frequency higher than 1.6 mhz, the cs pin must be deasserted to ensure a total d elay of 5 s; otherwise, the delay is not sufficient. when spi operation is enabled at 5 mhz, t he total delay necessary is at most 3.4 s. when i 2 c mode is enabled on the part, the communication rate is low enough to ensure a sufficient delay between fifo reads. self - test the adxl375 incorporates a self - test feature that effectively tests its mechanical and electronic systems simultaneously. when the self - test function is enabled (via the self_tes t bit in the data_format register, address 0x31), an electrostatic force is exerted on th e mechanical sensor. this electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the external acceleration experienced by the device. this added electrostatic force results in an output change in the x - , y - , and z - axes. because the electrostatic force is proportional to v s 2 , the output change varies with v s . the self - test response in the x - and y - axes exhibit s bimodal behavior and , therefore , is not always a reliable indicator of sensor health or potential shift in device sensitivity . for this reason , perform the self - test check in the z - axis. u se of the self - test feature at data rates of less than 100 hz or at 1600 hz may yield values outside the limits shown in figure 16. for the self - test function to operate correctly, the part must be in normal power operation (low_power bit = 0 in the bw_rate register, address 0x2c) and be configure d for a data rate from 100 hz to 800 hz , or for a data rate of 3200 hz (see table 6 ) . for more information about the self - test feature, see the using self - te st section.
data sheet adxl375 rev. 0 | page 13 of 32 interrupts the adxl375 provides two output pins for driving interrupts: int1 and int2. both interrupt pins are push - pull, low impedance pins ( see table 10 for output specification s). the default config - uration of the interrupt pins is active high. th e polarity can be changed to active low by setting the int_invert bit (bit d5) in the data_format register (address 0x31) . all interrupt functions can be enabled simultaneously , but som e functions ma y need to share the same interrupt pin. enabling and disabli ng interrupts interrupts are enabled by setting the appropriate bit s in the int_enable register (address 0x2e) ; the interrupt is mapped to the int1 pin or the int2 pin based on the c ontents of the int_map register (address 0x2f). when the user configur es the interrupt pins for the first time , it is recommended that the functions and interrupt mapping be configured before the interrupts are enabled . when changing the configuration of an interrupt, follow this procedure. 1. disable the interrupt by clearing the bit correspond ing to th e function in the int_enable register . 2. reconfigure the interrupt function . 3. reenable the interrupt in the int_enable register . configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt. clearing interrupts the interrupt functions are latched and can be cleared as follows: 1. r ead the data registers (address 0x32 to address 0x37) to clear the data - related inter rupts. 2. r ead the int_source register (address 0x30) to clear the remaining interrupts. bits in the interrup t registers this section describes the interrupts that can be set in the int_enable register (address 0x2e) and monitored in the int_sour ce register (address 0x30) . for an in - depth description of the fifo buffer and the inter - rupt bits, see the an - 1025 application note , utilization of the first in, first out (fifo) buffer in ana log devices, inc., digital accelerometers . data_ready bit the data_ready bit is set when new data is available and is cleared when no new data is available. single_ shock bit the single_ shock bit is set when a single acceleration event that is greater than the value in the thresh_ shock register (address 0x1d) occurs for less time than is specified by the dur register (address 0x21). for more information, see the shock detection section. double_ shock bit the double_ shock bit is set when two acceleration events that are greater than the value in the thresh_ shock register (address 0x1d) occur for less time than is specified by the dur register (address 0x21) . t he second shock event start s after the time specified by th e latent register (address 0x22) but within the time specified by the window register (address 0x23). for more information, s ee the shock detection section. activity bit the activity bit is set when acceleration g reater than the value stored in the thresh_act register (address 0x24) is experi - enced on any participating axis . participating axes are specified by the act_inact_ctl register (address 0x27). table 10 . interrupt pin digital output specifications limit 1 parameter test conditions/comments min max unit digital output low level output voltage (v ol ) i ol = 300 a 0.2 v dd i/o v high level output voltage (v o h ) i oh = ?150 a 0.8 v dd i/o v low level output current (i ol ) v o l = v ol, max 300 a high level output current (i oh ) v o h = v oh, min ?150 a pin c apacitance f in = 1 mhz, v s = 2.5 v 8 pf r ise /f all time c load = 150 pf rise time (t r ) 2 210 ns fall time (t f ) 3 150 ns 1 limits based on characterization results ; not production tested. 2 rise time is measured as the transition tim e from v ol, max to v oh, min of the interrupt pin. 3 fall time is measured as the transition time from v oh, min to v ol, max of the interrupt pin.
adxl375 data sheet rev. 0 | page 14 of 32 inactivity bit the inactivity bit is s et when acceleration less than the value stored in the thresh_inact register (address 0x25) is experienced for more time than is specified by the time_inact register (address 0x26) on all participating axes. participating axes are specified by the act_inac t_ctl register (address 0x27). the maximum value for time_inact is 255 sec. watermark bit the watermark bit is set when the number of samples in the fifo buffer equals the value stored in the samples bits (bits[d4:d0]) of the fifo_ctl register (address 0x3 8). the watermark bit is cleared automatically when the fifo buffer is read and the fifo content s return to a value below the value s pecified by the samples bits. overrun bit the overrun bit is set when new data replaces unread data. the precise operatio n of the overrun function depends on the fifo mode (see the fifo buffer section). ? in bypass mode, the overrun bit is set when new data replaces unread data in the data registers (address 0x32 to address 0x37). ? in fifo mode , strea m mode, and trigger mode , the overrun bit is set when the fifo buffer is full . the overrun bit is automatically cleared when the fifo buffer contents are read.
data sheet adxl375 rev. 0 | page 15 of 32 serial communication s the adxl 375 supports i 2 c and spi digital communications. in both cases, the adxl375 operates as a slave device . when the cs pin is tied high to v dd i/o , i 2 c mode is enabled. the cs pin must be tied high to v dd i/o or be driven by an external controller . i f the cs pin is left unconnected , the user may not be able to com muni - cate with the part. in spi mode, the cs pin i s controlled by the bus master. in both spi and i 2 c modes of operation, ignore data transmitted from the adxl375 to the master device during writes to the adxl375 . spi mode the adxl375 can be configured for 3 - wire spi mode or 4 - wire spi mode , as shown in figure 22 and figure 23 . clearing the spi bit (bit d6) in the data_format register (address 0x31) selects 4 - wire mode ; setting the spi bit selects 3 - wire mode. the maxi - mum spi clock speed is 5 mhz with 100 pf maximum loading . t he timing scheme requires clock polarity (cpol) = 1 and clock phase (cpha) = 1. if power is applied to the adxl375 before the clock polarity and phase of the host processor are configured, take the cs pin high before changing the clock polarity and phase. when using 3 - wire spi mode , it is recommended that the sdo pin be either pulled up to v dd i/o or pulled down to gnd via a 10 k? resistor. processor d out d in/out d out adxl375 cs sdio sdo sclk 1 1669-004 figure 22 . 3 - wire spi connection diagram processor d out d out d in d out adxl375 cs sdi sdo sclk 11669-003 figure 23 . 4 - wire spi connection diagram cs is the serial port enable line and is controlled by the spi master. this line mus t go low at the start of a transmission and high at the end of a transmission, as shown in figure 25 to figure 27. sclk is the serial port clock and is supplied by the spi master. sclk should idle high during a period of no transmission. in 4 - wire spi mode, sdi and sdo are the serial data input and output, respectively. in 3 - wire spi mode, sdio functions as both the serial data input and output. data is updated on the fallin g edge of sclk and should be sampled on the rising edge of sclk. to read or write multiple bytes in a single transmission, the multiple - byte bit (mb in figure 25 to figure 27) , located after the r/ w bit in the first byte transfer, must be set. after the register address byte and the first byte of data, each subsequent set of eight clock pulses causes the adxl375 to point to the next register for a read or write. this shifting continues until the clock pulses cease and cs is deasserted. to perform reads or writes on different, nonsequential registers, c s must be deasserted between transmissions and the new register must be addressed separately. figure 25 and figure 26 show the timing diagrams for 4 - wire spi writes an d reads, respectively. figure 27 shows the timing diagram for 3 - wire spi reads or writes . for correct operation of the part, the logic thresholds and timing parameters in table 11 and table 12 must be met at all times. use of the 3200 hz and 1600 hz output data rates is recom - mended only with spi communication speeds greater than or equal to 2 mhz. the 800 hz output data rate is reco mmended only with communication speeds greater than or equal to 400 khz, and the remaining data rates scale proportionally. for example, the minimum recommended communication speed for a 200 hz output data rate is 100 khz. operation at an output data rate above the recommended maximum value may result in undesirable effects on the acceleration data, including missing samples or additional noise. preventing bus traffic errors the adxl375 cs pin is used both for initiating spi transactions and for enabling i 2 c mode. when the adxl375 is used on a spi bus with multiple devices, its cs pin is held hi gh while the master communicates with the other devices. there may be conditions where a spi command transmitted to another device looks like a valid i 2 c command. in this case, the adxl375 interp ret s this command as an attempt to communicate in i 2 c mode and may interfere with other bus traffic. unless bus traffic can be ade - quately controlled to en sure that such a condition never occurs, it is recommended that a logic gate be ad de d in front of pin 13 (sda/sdi/sdio) , as shown in figure 24 . this or gate hold s the sda line high when cs is high to prevent spi bus traffic at the a dxl375 from appearing as an i 2 c start command. processor d out d in/out d in d out adxl375 cs sda/sdi/sdio sdo sclk 11669-104 figure 24 . recommended spi connection diagram when using multiple spi devices on a single bus
adxl375 data sheet rev. 0 | page 16 of 32 1 1669-017 t del a y t setu p t hold t sdo x x x w mb a5 a0 d7 d0 x x x address bits dat a bits t sclk t m t s t quiet t dis t cs, dis sclk sdi sdo cs figure 25 . spi 4 - wire write timing diagram 1 1669-018 cs x x x r mb a5 a0 d7 d0 x x x address bits dat a bits t dis sclk sdi sdo t quiet t cs, dis t sdo t setu p t hold t del a y t sclk t m t s figure 26 . spi 4 - wire read timing diagram 1 1669-019 cs t del a y t setu p t hold t sdo r/w mb a5 a0 d7 d0 address bits d at a bits t sclk t m t s t quiet t cs, dis sclk sdio notes 1. t sdo is on l y present during reads. figure 27 . spi 3 - wire read/write timing diagram
data sheet adxl375 rev. 0 | page 17 of 32 table 11 . spi digital input/output specifications limit 1 parameter test conditions/c omments min max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage ( v ih ) 0.7 v dd i/o v low level input current ( i il ) v s = v dd i/o 0.1 a high level input current ( i ih ) v s = 0 v ?0.1 a digital output low level output voltage ( v o l ) i o l = 10 ma 0.2 v dd i/o v high level output voltage ( v oh ) i oh = ?4 ma 0.8 v dd i/o v low level output current ( i o l ) v o l = v ol , max 10 ma high level output current ( i oh ) v oh = v o h, min ?4 ma pin c apacitance f in = 1 mhz, v s = 2.5 v 8 pf 1 limits based on characterization results ; not production tested. table 12 . spi timing (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) 1 limit 2 , 3 parameter min max unit description f sclk 5 mhz spi clock frequency t sclk 200 ns m ark - space ratio ( 1/(spi clock frequency ) ) for t he sclk input is 40/60 to 60/40 t delay 5 ns cs fa lling edge to sclk falling edge t quiet 5 ns sclk rising edge to cs rising edge t dis 10 ns cs rising edge to sdo/sdio disabled t cs , dis 150 ns cs deasser tion between spi communications t s 0.3 t sclk ns sclk low pulse width (space ) t m 0.3 t sclk ns sclk high pulse width (mark) t setup 5 ns sd i/sdio valid before sclk rising edge t hold 5 ns sd i/sdio valid after sclk r ising edge t sdo 40 ns sclk falling edg e to sdo/sdio output transition t r 4 20 ns sdo/sdio output high to output low transition t f 4 20 ns sdo/sdio output low to output high transition 1 the cs , sclk, sdi, a nd sdo pins are not internally pulled up or down; they must be driven for proper operation. 2 limits based on characterization results, with f sclk = 5 mhz and bus load capacitance of 100 pf; not production tested. 3 the timing values are referred to the in put thresholds (v il and v ih ) given in table 11. 4 output rise and fall times measured with capacitive load of 150 pf. t r and t f are not shown in figure 25 to figure 27.
adxl375 data sheet rev. 0 | page 18 of 32 i 2 c mode w hen t he cs pin is tied high to v dd i/o , the adxl375 is configured for i 2 c mode . i 2 c mode requires a simple 2 - wire connection, as shown in figure 28 . the adxl375 conforms to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007, available from nxp semiconductor s . the adxl375 supports s tandard (100 khz) and fast (400 khz) data transfer modes if the bus parameters given in table 13 and table 14 are met. single - or multipl e - byte reads and writes are supported, as shown in figure 29. w hen the alt address pin (pin 12 ) is tied high to v dd i/o , the 7 - bit i 2 c address for the device is 0x1d, followed by the r/ w bit. in this configuration, the write address is 0x3a , and the read address is 0x3b. an alternate i 2 c address of 0x53 can be selected by grounding the alt address pin ( see figure 28). in this configuration, the write a ddress is 0xa6 , and the read address is 0xa7. u nused pins have no internal pull - up or pull - down resistors; therefore, the cs and alt address pin s have no known state or default state if the pins are left floating or unconnected. when using i 2 c mode, i t is required that the cs pin be connected to v dd i/o and that the alt address pin be connected to either v dd i/o or gnd. processor d in/out d out r p v dd i/o r p adxl375 cs sda alt address scl 11669-008 figure 28 . i 2 c connection diagram (address 0x53) due to communicatio n speed limitations, the maximum output data rate when using 400 khz i 2 c mode is 800 hz , which scales linearly with a change in the i 2 c communication speed. for example, using i 2 c mode at 100 khz limit s the maximum odr to 200 hz. operation at an output dat a rate above the recom - mended maximum value may result in undesirable effects on the acceleration data, including missing samples or additional noise. if other devices are connected to the same i 2 c bus, the nominal operating voltage level of the other devi ces cannot exceed v dd i/o by more than 0.3 v. external pull - up resistors, r p , are necessary for proper i 2 c operation (see figure 28 ) . to ensure proper opera - tion, r efer to the um10204 i 2 c - bus specification and user manual , rev. 03 19 june 2007, when selecting pull - up resistor values. notes 1. the shaded areas represent when the device is listening. 1 this s t art is either a repe a ted s t art or a s t op followed b y a s t ar t . master st art sl a ve address + write register address sl a ve ack ack ack master st art sl a ve address + write register address sl a ve ack ack ack ack master st art sl a ve address + write register address st op sl a ve ack ack master st art st art 1 st art 1 sl a ve address + write register address nack st op sl a ve ack ack dat a st op ack single-byte write mu l tiple-byte write dat a dat a mu l tiple-byte read sl a ve address + read sl a ve address + read ack dat a dat a dat a st op nack ack single-byte read 1 1669-033 figure 29 . i 2 c device addressing table 13. i 2 c digital input/output specifications limit 1 parameter test conditions/comments mi n max unit digital input low level input voltage (v il ) 0.3 v dd i/o v high level input voltage (v ih ) 0.7 v dd i/o v low level input current ( i il ) v s = v dd i/o 0.1 a high level input current ( i ih ) v s = 0 v ?0.1 a digital output low level out put voltage (v o l ) v dd i/o < 2 v, i ol = 3 ma 0.2 v dd i/o v v dd i/o 2 v, i ol = 3 ma 400 mv low level output current ( i o l ) v o l = v ol, max 3 ma pin c apacitance f in = 1 mhz, v s = 2.5 v 8 pf 1 limits based on characterization results; not production tested.
data sheet adxl375 rev. 0 | page 19 of 32 table 14. i 2 c timing (t a = 25c, v s = 2.5 v, v dd i/o = 1.8 v) limit 1 , 2 parameter min max unit description f scl 400 khz scl clock frequency t 1 2.5 s scl cycle time t 2 0.6 s scl high time t 3 1.3 s scl low time t 4 0.6 s h old time for start/ repeated start condition t 5 100 ns d ata setup time t 6 3 , 4 , 5 0 0.9 s d ata hold time t 7 0.6 s s etup time for repeated start condition t 8 0.6 s s etup time for stop condition t 9 1.3 s b us - free time between a stop condition and a start condition t 10 300 ns r ise time of scl and sda when receiving 0 ns r ise time of scl and sda when receiving or transmitting t 11 300 ns f all time of scl and sda when receiving 250 ns f all time of scl and sda when transmitting c b 400 pf capacitive load for each bus line 1 limits based on characterization results, with f scl = 400 khz and a 3 ma sink current; not production tested. 2 the timing values are referred to the input thresholds (v il and v ih ) given in table 13. 3 t 6 is the data hold time that is measured from the falling edge of scl. it applies to data during the transmission and acknowledge phases . 4 t o bridge the undefined region of the falling edge of scl , a transmitting device must internally provide an output hold time of at least 300 ns for the sda signal (with respect to v ih , min of the scl signal). 5 the maximum value for t 6 must be met only if the device does not stretch the low period (t 3 ) of the scl signal. the maximum value for t 6 is a function of the clock low time (t 3 ), the clock rise time (t 10 ), and the minimum data setup time (t 5 (min ) ). this value is calculated as t 6 (max ) = t 3 ? t 10 ? t 5 (min ) . sd a t 9 sc l t 3 t 10 t 1 1 t 4 t 4 t 6 t 2 t 5 t 7 t 1 t 8 s t art condition repe a ted s t art condition s t o p condition 11669-034 figure 30 . i 2 c timing diagram
adxl375 data sheet rev. 0 | page 20 of 32 register map all registers in the adxl375 are eight bits in length. table 15. regis ter map address register name access type hex dec imal reset value description 0x00 0 devid r 11100101 device id 0x01 to 0x1c 1 to 28 reserved n/a n/a reserved; do not access 0x1d 29 thresh_ shock r/ w 00000000 shock threshold 0 x1e 30 ofsx r/ w 00000000 x - axis offset 0x1f 31 ofsy r/ w 00000000 y - axis offset 0x20 32 ofsz r/ w 00000000 z - axis offset 0x21 33 dur r/ w 00000000 shock duration 0x22 34 latent r/ w 00000000 shock latency 0x23 35 window r/ w 00000000 shock window 0x24 36 thresh_act r/ w 00000000 activity threshold 0x25 37 thresh_inact r/ w 00000000 in activity threshold 0x26 38 time_inact r/ w 00000000 inactivity time 0x27 39 act_inact_ctl r/ w 00000000 axis enable control for activity and inactivity detection 0x2a 42 shock _axes r/ w 0000 0000 axis control for single shock /double shock 0x2b 43 act_ shock _status r 00000000 source of single shock /double shock 0x2c 44 bw_rate r/ w 00001010 data rate and power mode control 0x2d 45 power_ctl r/ w 00000 000 power saving features control 0x2e 46 int_enable r/ w 00000000 interrupt enable control 0x2f 47 int_map r/ w 00000000 interrupt mapping control 0x30 48 int_source r 00000010 in terrupt source 0x31 49 data_fo rmat r/ w 00000000 data format control 0x32 50 datax0 r 00000000 x - axis data 0 0x33 51 datax1 r 00000000 x - axis data 1 0x34 52 datay0 r 00000000 y - axis data 0 0x35 53 datay1 r 00000000 y - axis data 1 0x36 54 dataz0 r 00000000 z - axi s data 0 0x37 55 dataz1 r 00000000 z - axis data 1 0x38 56 fifo_ctl r/ w 00000000 fifo control 0x39 57 fifo_status r 00000000 fifo status
data sheet adxl375 rev. 0 | page 21 of 32 register descriptions all registers in the adxl375 are eight bits in length. register 0x00devid (read only) d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 0 0 1 0 1 the read-only devid register holds the fixed device id code of 0xe5 (345 octal). register 0x1dthresh_shock (read/write) the thresh_shock register contains the unsigned threshold value for shock interrupts. the magnitude of the shock event is compared with the value in the thresh_shock register for shock detection. the scale factor is 780 m g /lsb. a value of 0 may result in undesirable behavior if single shock/double shock inter- rupts are enabled. register 0x1e, register 0x1f, register 0x20ofsx, ofsy, ofsz (read/write) the ofsx, ofsy, and ofsz registers contain user-configured offset adjustments in twos complement format with a scale factor of 1.56 g /lsb. the value stored in the offset registers is automat- ically added to the acceleration data, and the resulting value is stored in the output data registers (address 0x32 to address 0x37). for more information about offset calibration and the use of the offset registers, see the offset calibration section. register 0x21dur (read/write) the dur register contains an unsigned time value representing the maximum time that an event must be above the thresh_ shock threshold to qualify as a shock event. the scale factor is 625 s/lsb. a value of 0 disables the single shock and double shock functions. register 0x22latent (read/write) the latent register contains an unsigned time value representing the wait time from the detection of a shock event to the start of the time window (specified by the window register) during which a possible second shock event can be detected. the scale factor is 1.25 ms/lsb. a value of 0 disables the double shock function. register 0x23window (read/write) the window register contains an unsigned time value repre- senting the amount of time after the expiration of the latency time (specified by the latent register) during which a second valid shock can begin. the scale factor is 1.25 ms/lsb. a value of 0 disables the double shock function. register 0x24thresh_act (read/write) the thresh_act register contains the unsigned threshold value for detecting activity. the magnitude of the activity event is compared with the value in the thresh_act register. the scale factor is 780 m g /lsb. a value of 0 may result in undesirable behavior if the activity interrupt is enabled. register 0x25thresh_inact (read/write) the thresh_inact register contains the unsigned threshold value for detecting inactivity. the magnitude of the inactivity event is compared with the value in the thresh_inact register. the scale factor is 780 m g /lsb. a value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. register 0x26time_inact (read/write) the time_inact register contains an unsigned time value representing the amount of time that acceleration must be less than the value in the thresh_inact register for inactivity to be detected. the scale factor is 1 sec/lsb. unlike the other interrupt functions, which use unfiltered output data (see the threshold detection and bandwidth section), the inactivity function uses filtered output data. at least one output sample must be generated for the inactivity interrupt to be triggered. for this reason, the inactivity function may appear to be unresponsive if the time_inact register is set to a value less than the time constant of the output data rate. a value of 0 results in an interrupt when the output data is less than the value in the thresh_inact register. the maximum value for time_inact is 255 sec. register 0x27act_inact_ctl (read/write) d7 d6 d5 d4 act ac/dc act_x enable act_y enable act_z enable d3 d2 d1 d0 inact ac/dc inact_x enable inact_y enable inact_z enable the act_inact_ctl register selects dc-coupled or ac-coupled operation and selects the axes that participate in activity and inactivity detection. act ac/dc and inact ac/dc bits a setting of 0 for the act ac/dc and inact ac/dc bits selects dc-coupled operation; a setting of 1 selects ac-coupled operation. in dc-coupled operation, the current acceleration magnitude is compared directly with the values in the thresh_ act and thresh_inact registers to determine whether activity or inactivity is detected. in ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. new samples of acceleration data are then compared to this ref- erence value and, if the magnitude of the difference exceeds the thresh_act value, an activity interrupt is triggered. similarly, in ac-coupled operation for inactivity detection, a refer- ence value is used for comparison and is updated whenever the device exceeds the inactivity threshold. after the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with the thresh_inact value. if the difference is less than the value in the thresh_inact register for the time specified in the time_inact register, the device is considered inactive, and the inactivity interrupt is triggered.
adxl375 data sheet rev. 0 | page 22 of 32 act_x enable and inact_x enable bits a setting of 1 for the act_x enable and inact_x enable bits enables x - , y - , or z - axis participation in detecting activity or inac tivity. a setting of 0 excludes the selected axis from participa - tion. if all axes are excluded, the function is disabled. for activity detection, all participating axes are logically ored, causing the activity function to be trigger ed when any participat ing ax i s exceeds the activity threshold. for inactivity detection, all parti - cipating axes are logically anded, causing the inactivity function to be trigger ed only if all participating axes are below the inactivity threshold for the specified time. regis ter 0x2a shock _axes ( read/write ) d7 d6 d5 d4 0 0 0 0 d3 d2 d 1 d0 suppress shock _ x enable shock _ y enable shock _z enable the shock _axes register specifies the participation of each of the three axes in single shock /double shock detection. suppress bit se tting the suppress bit suppresses double shock detection if acceleration greater than the value in the thresh_shock register is present during the latency time between shocks . for more information, s ee the shock detection section. shock _x enable bits a setting of 1 in the shock _x enable, shock _y enable, or shock _z enable bit enables x - , y - , or z - axis participation in shock detection. a setting of 0 excludes the selected axis from participation in shock detection. re gister 0x2b act_ shock _status (read only) d7 d6 d5 d4 0 act_x source act_y source act_z source d3 d2 d 1 d0 asleep shock_x source shock_y source shock _z source the read - only act_ shock _status register indicates the first axis involved in a n activity or sh ock event. act _x source and shock _x source bits the act_x s ource and shock_x s ource b its indicate the first axis involved in a n activity or shock event . a setting of 1 corresponds to involvement in the event ; a setting of 0 corre - sponds to no involvement. when new data is available, these bits are not cleared but are overwritten by the new data. read the act_ shock _status register before clearing the inter - rupt. disabling an axis from participation in activity or shock events clears the corresponding source bit in this register when the next activity or single shock /double shock event occurs. asleep bit a setting of 1 in the asleep bit indicates that the part is asleep ; a setting of 0 indicates that the part is not asleep. this bit toggles only if th e de vice is configured for auto sleep. f or more informa - tion about the autosleep mode, s ee the auto_sleep bit section. register 0x2c bw_rate ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 low_power rate the bw_rate regist er configures the device bandwidth and output data rate ; this register also enables and disables low power mode. low _power bit a setting of 0 in the low_power bit selects normal opera - tion ; a setting of 1 selects reduced power operation, which has somewh at higher noise . for more information, see the low power mode section. rate bits the rate bits select the device bandwidth and output data rate (see table 6 and table 8 ). the default value for these bits is 0x0a, which translates to a 100 hz output data rate. the selected output data rate must be appropriate for the communication protocol and frequency selected. selecting an output data rate that i s too high for the communication speed may result in samples being discarded (for more information, see the serial communications section). register 0x2d power_ctl ( read/write ) d7 d6 d5 d4 d3 d2 d1 d0 0 0 link aut o_sleep measure sleep wakeup the power_ctl register can be used to configure the device for auto sleep mode ; this register is also used to set the device to measurement mode or standby mode. link bit th e link bit serially links the activity and inactivity functions. if both the activity and inactivity functions are enabled, a setting of 1 in the link bit delays the start of the activity detection function until inactivity is detected. after activity is detected, inactivity detection begins, preventing the d etection of activity. when this bit is set to 0, the inactivity and activity functions are concurrent. for more information about the link feature , see the link mode section. before clearing the link bit, it is rec ommended that the part be placed in standby mode (set the measure bit, bit d3, to 0). after clearing the link bit, reset the part to measurement mode (set the measure bit, bit d3, to 1). this configuration sequence ensures that the device is properly biase d if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device is asleep when the bit is cleared.
data sheet adxl375 rev. 0 | page 23 of 32 auto_sleep bit if the link bit is set, a setting of 1 in th e auto_sleep bit enables the auto sleep function. in autosleep mode, the adxl375 auto matically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, whe n acceleration is below the thresh_inact value for at least the time specifi ed by the time_inact value ). if activity detection is also enabled, the adxl375 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the bw_rate register. a setting of 0 in the auto_sleep bit disables aut omatic switching to sleep mode. if the link bit is not set, the auto_sleep feature is disabled and setting th e auto_sleep bit has no effect on device operation. for more information about the link feature , see the link bit section and the link mode section. for more information about autosleep mo de, see the autos leep mode section. before clearing the auto_sleep bit, it is recommended that the part be placed in standby mode (set the measure bit, bit d3, to 0) . after clearing the auto_sleep bit, reset the part to measure - me nt mode (set the measure bit, bit d3, to 1) . this configuration sequence ensure s that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the auto_sleep bit is cleared may have additional noise, especially if the device is asleep when the bit is cleared. measure bit a setting of 0 in the measure bit places the part into standby mode ; a setting of 1 places the part into measurement mode. the adxl375 powers up in standby mode with minimum power consumption (see the power sequencing section) . sleep bit a setting of 0 in the sleep bit p laces the part into the normal mode of operation ; a setting of 1 places the part i nto sleep mode. sleep mode suppresses the data_ready interrupt , stops trans - mission of data to the fifo buffer , and switches the sampling rate to the rate specified by the wakeup bits (bits[d1:d0]) . in sleep mode, only the activity function can be used. wh en the data_ready interrupt is suppressed, the output data registers (register 0x32 to register 0x37) are still updated at the sampling rate set by the wakeup bits. before clearing the sleep bit, it is recommended that the part be placed in standby mode (s et the measure bit, bit d3, to 0). after clearing the sleep bit, reset the part to measurement mode (set the measure bit, bit d3, to 1) . wa k eu p bits the wakeup bits control the sampling rate during sleep mode (see table 16). table 16. sampling rate in sleep mode setting d1 d0 frequency (hz) 0 0 8 0 1 4 1 0 2 1 1 1 register 0x2e int_enable ( read/write ) d7 d6 d5 d4 data_ready single_shock double_shock activity d3 d2 d1 d0 inactivi ty 0 watermark overrun a s etting of 1 for any bit in th e int_enable register enables the specified function to generate interrupts ; a setting of 0 for any bit in this register prevents the function from generating interrupts. the data_ready, watermark, an d overrun bits enable only the interrupt output; the functions are always enabled. it is recommended that interrupts be configured in register 0x2f before their outputs are enabled in this register . for more information about the interrupts, see the bits in the interrupt registers section. register 0x2f int_map ( read/write ) d7 d6 d5 d4 data_ready single_ shock double_ shock activity d3 d2 d1 d0 inactivity 0 watermark overrun a s etting of 0 for any bit in th e int_m ap register causes the specified interrupt to be sent to the int1 pin; a setting of 1 for any bit in this register causes the specified interrupt to be sent to the int2 pin . all selected interrupts for a given pin are ored. register 0x30 int_source (read only) d7 d6 d5 d4 data_ready single_shock double_shock activity d3 d2 d1 d0 inactivity x 1 watermark overrun 1 x = ignore this bit. a setting of 1 for any bit in the int_source register indicates that the specified function has triggered an interrupt; a setting of 0 for any bit in this register indicates that the specified function has not triggered an interrupt. the data_ready, watermark, and overrun bits are always set if the corresponding interrupt occur s , regardless of the settings in the int_enable register ; these bits are cleared by reading data from the data registers ( address 0x32 to address 0x37) . the data_ready and water - mark bits may require multiple reads to be cleared . other bits, and the ir corresponding interrupts, are cleared by reading th e int_source register.
adxl375 data sheet rev. 0 | page 24 of 32 register 0x31 data_format (read/write) d7 d6 d5 d4 d3 d2 d1 d0 self_test spi int_invert 0 1 justify 1 1 the data_format register controls the presentation of data to register 0x32 through register 0x37. self_test bit a setting of 1 in the self_test bit applies a self - test force to the sensor, causing a shift in the output data. a value of 0 disables the self - test force. for more information about the self - test function, see the self - te st s ection and the using self - te st section. spi bit a value of 1 in the spi bit configures the device for 3 - wire spi mode ; a value of 0 configures the device for 4 - wire spi mode. int_invert bit a value of 0 in the int_ invert bit sets the polarity of the interrupt pin s to active high ; a value of 1 sets the polarity of the interrupt pin s to active low. justify bit a setting of 1 in the justify bit selects left justified (msb) mode ; a setting of 0 selects right just ified (lsb) mode with sign extension. register 0x32 to register 0x37 datax0, datax1, datay0, datay1, dataz0, dataz1 (read only) these six bytes (register 0x32 to register 0x37) are each eight bits in length and contain the output data for each axis. ? register 0x 32 and register 0x33 contain the output data for the x - axis . ? register 0x34 and register 0x35 contain the output data for the y - axis . ? register 0x36 and register 0x37 contain the output data for the z - axis. the output data is in twos complement format . da tax0 is the least significant byte , and datax1 is the most significant byte ( x represent s x, y, or z ) . the data_format register (address 0x31) controls the format of the data. it is recommended that a multiple - byte read of all six registers be performed t o prevent a change in data between reads of sequential registers. when using the 3200 hz or 1600 hz output data rate, the lsb of the output data - word is always 0. when the data is right justified, the lsb corresponds to bit d0 of the datax0 register; when the data is left justified, the lsb corresponds to bit d3 of the datax0 register. register 0x38 fifo_ ctl (read/write) d7 d6 d5 d4 d3 d2 d1 d0 fifo_mode trigger samples the fifo _ctl register is used to configure the fifo buffer for the device. for mo re information, see the fifo buffer section. for an in - depth description of the fifo buffer, see the an - 1025 application note , utilization of the first in, first out ( fifo) buffer in analog devices, inc., digital accelerometers . fifo_mode bits these bits set the fifo mode, as described in table 17. table 17 . fifo modes setting fifo mode d 7 d 6 description 0 0 bypass f ifo buffer is bypassed. 0 1 fifo fifo buffer collects up to 32 samples and then stops collecting data, collecting new data only when the buffer is not full. 1 0 stream fifo buffer holds the last 32 samples. when the buffer is full, the oldest data is ov erwritten with newer data. 1 1 trigger fifo buffer holds the last samples before the trigger event and continues to collect data until full. new data is collected only when the buffer is not full. trigger bit a value of 0 in the trigger bit links the tri gger event of trigger mode to the int1 pin , and a value of 1 links the trigger event to the int 2 pin . samples bits the function of the samples bits depends on the fifo mode selected (see table 18 ). entering a valu e of 0 in the samples bits immediately sets the watermark bit in the int_source register, regardless of the fifo mode selected. undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. table 18. samples bits functions fifo mode sample s bits f unction bypass none. fifo specifies how many fifo entries are needed to trigger a watermark interrupt. stream specifies how many fifo entries are needed to trigger a watermark interrupt. trigger specifies how many fifo samples are retained in the fifo buffer before a trigger event.
data sheet adxl375 rev. 0 | page 25 of 32 register 0x39 fifo_status (read only) d7 d6 d 5 d4 d3 d2 d1 d0 fifo_trig 0 entries the read - only fifo_status register indicates whether a trigger event has occur red and reports the number of data values stored in the fifo buffer. fifo_ trig bit when the fifo_trig bit is set to 1, a trigger event has occurr ed; when the fifo_trig bit is set to 0 , no trigger event has occurred. entries bits the entries bits report h ow many data values are stored in the fifo buffer . t he data stored in the fifo buffer is accessed by reading the data registers (address 0x32 to address 0x37) . fifo reads must be done in burst mode ( multiple - byte mode ) because each fifo level is cleared af ter any read (single - or multiple - byte) of the fifo buffer . the fifo buffer stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device.
adxl375 data sheet rev. 0 | page 26 of 32 applications informa tion power supply decoupl ing a 1 f tantalum capacitor (c s ) at v s and a 0.1 f ceramic capac - itor (c i/o ) at v dd i/o placed close to the adxl375 supply pins are recommended t o adequately decouple the accelerometer from noise on the power supply. if additional decoupling is necessary, a resistor or ferrite bead ( no larger than 100 ? ) in series with v s may be helpful. additionally, increasing the bypass capacitance on v s to a 10 f tantalum capacitor in parallel with a 0.1 f ceramic ca pacitor may also improve noise performance . make sure that the connection from the adxl375 ground to the power supply ground has low imp edance because noise trans - mitted through ground has an effect similar to noise transmitted through v s . it is recommended that v s and v dd i/o be separate supplies to minimize digital clocking noise on the v s supply. if it is not possible to use separate su pplies , additional filtering of the supplies, as previously mentioned, may be necessary. 1 1669- 016 adxl375 gnd int1 int2 cs scl/sclk sdo/a l t address sda/sdi/sdio 3- or 4-wire spi or i 2 c inter f ace v s v s c s v dd i/o v dd i/o c i/o interrupt contro l figure 31 . application diagram mechanical considera tions for mounting mount t he adxl375 on the pcb in a location close to a hard mounting point of the pcb to the case. mounting the adxl375 at an unsupported pcb location, as shown in figure 32 , may result in large, apparent measurement errors due to undampened pcb vibration. locating the accelerometer near a hard mounting point ensures that any pcb vibration at the accelerometer is above the mechanical sensor resonant frequency of th e accelerometer and is , therefore, effectively invisible to the accelerometer. multiple mounting points, close to the sensor, and/or a thicker pcb also help to reduce the effect s of system resonance on the performance of the sensor. mounting points pcb accelerometers 11669-036 figure 32 . incorrectly placed accelerometers shock detection the shock interrupt function can detect mechanical shock events based on amplitude and pulse width . figure 33 illustrates t he following parameters for a valid sin gle shock event and a valid double shock event. ? shock detection threshold defined by the thresh_ shock register (address 0x1d). ? maximum shock duration time (time limit for shocks) defined by the dur register (address 0x21). ? shock latency tim e defined by the latent register (address 0x22) . the latency time is the waiting period from the end of the first shock until the start of the time window, when a second shock can be detected . ? time window for second shock defined by the window register (ad dress 0x23). the time window is the i nterval after the latency time (set by the latent register). although a second shock must begin after the latency time expires , it need not finish before the end of the time defined by the window register. first shock time limit for shocks (dur) la tenc y time (l a tent) time window for second shock (window) second shock single shock interrupt double shock interrupt threshold (thresh_shock) acceler a tion interrupts 1 1669-037 figure 33 . shock interrupt function with valid single and double shocks if only the single shock function is in use, the single shock interrupt is triggered when the acceleration goes below the threshold, as long as the duration time is not e xceeded. if both the single and double shock functions are in use, the single shock interrupt is triggered when the double shock event is either validated or invalidated.
data sheet adxl375 rev. 0 | page 27 of 32 several events invalidate the se cond shock of a double shock event. ? i f the suppre ss bit in the shock _axes register ( bit d3, address 0x2a) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidates the double shock detection (see figure 34). in v alid a tes double shock if suppress bit set time window for second shock (window) l a tenc y time (l a tent) time limit for shocks (dur) 1 1669-038 acceler a tion figure 34 . double shock event invalid due to high g event when the suppress bit is set ? a double shock event can be invalidated if acceleration above the threshold is detected at the start of the time window for the second sho ck (set by the window register) , resulting in an invalid double shock at the start of this window (see figure 35). ? a double shock event can be invalidated if acceleration exceeds the time limit for shocks (set by the dur register), resulting in an invalid double shock at the end of the dur time limit for the second shock event (see figure 35). in v alid a tes double shock a t s t art of window time window for second shock (window) la tenc y time (l a tent) in v alid a tes double shock a t end of dur time limit for shocks (dur) time limit for shocks (dur) time limit for shocks (dur) 1 1669-039 acceler a tion acceler a tion figure 35 . shock interrupt function with invalid doub le shocks single shocks , double shocks , or both can be detected by setting the appropriate bits in the int_enable register (address 0x2e). p articipation of each of the three axes in single shock /double shock detection is controlled by setting the appropri ate bits in the shock _axes register (address 0x2a). for the double shock function to operate, both the latent and window registers must be set to a nonzero value. every mechanical system has somewhat different shock responses based on the mechanical charac teristics of the system. therefore, some experimentation with values for the dur, latent, window, and thresh_ shock registers is required. setting a very low value in the latent, window, or thresh_ shock register can result in unpredictable response s due to the accelerometer picking up echoes of the shock inputs. after a shock interrupt is received, the first axis to exceed the thresh_ shock level is reported in the act_ shock _ status register (address 0x2b). this register is never cleared but is overwritten w ith new data. threshold detection and bandwi dth l ower output data rates are achieved by decimating a common sampling frequency inside the device. the ac tivity and single shock /double shock detection functions are performed using undecimated data. because t he bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high g data that is used to determine activity and single shock /double shock events may not be present if the output o f the accelerometer is examined. this may result in the triggering of these functions when acceleration data does not appear to meet the conditions set by the user for the corresponding function. link mode the link bit (bit d5 ) in the power_ctl register ( a ddress 0x2d) can be used to reduce the number of activity interrupts that the processor must service . the link bit configures t he device to look for activity only after inactivity. for proper operation of this feature, the processor must still respond to t he activity and inactivity interrupts by reading the int_source register (address 0x30) and, therefore, clearing the interrupts. if an activity interrupt is not cleared, the part cannot enter autosleep mode. the asleep bit (bit d3) in the act_ shock _status register ( address 0x2b) indicates whether the part is asleep.
adxl375 data sheet rev. 0 | page 28 of 32 sleep mode vs . low power mode in applications where a low data rate and low power consumption are desired (at the expense of noise performance), it is recom - mended that low power mode be u sed. l ow power mode preserves the functionality of the data_ready interrupt and the fifo buffer for postprocessing of the acceleration data. to enable low power mode, set the low_power bit (bit d4) in the bw_rate register (address 0x2c). sleep mode also pr ovides a low data rate and low power consump - tion, but i t i s not intended for data acquisition. however, when sleep mode is used in conjunction with the autosleep and link mode s , the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. to prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and the activity interrupt is enabled. to enable autosleep mode, set the auto_sleep bit (bit d4) and the link bit (bit d5) in the power_ctl register (address 0x2d). when the adxl375 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. when ac tivity is detected, the accelerometer auto - matically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. similar to when inactivity occurs, detection of activity even ts is disabled and detection of inactivity is en abled. offset calibration accelerometers are mechanical structures containing elements that are free to move. these moving parts can be very sensitive to mechanical stresses, much more so than solid - state ele ctronics. the 0 g bias , or offset, is an important accelerometer metric because it defines the baseline for measuring acceleration. additional stresses can be applied during assembly of a system containing an accelerometer. these stresses can come from, b ut are not limited to, component soldering, board stress during mounting, and application of any compounds on or over the component. if calibration is deemed necessary, it is recommended that it be performed after system assembly to compensate for these ef fects. a simple method of calibration is to measure the offset while assuming that the sensitivity of the adxl375 is as specified in table 1 . the offset can then be automatically accounted for by using the built - in offset registers. the result of t his calibration is that the data acquired from the data registers already compensates for any offset. in a no - turn or single - point calibration scheme, the part is oriented such that one axis, typically the z - axis, is in the 1 g field of gravity , and the remaining axes, typically the x - and y - ax e s, are in a 0 g field. the output is then measured by taking the average of a series of samples. the number of samples averaged is selected by the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 hz or greater that is, 10 samples at the 100 hz data rate. for data rates less than 100 hz, it is recom - mended that at least 10 sam ples be averaged. these values are stored as x 0 g , y 0 g , and z +1 g for the 0 g measurements on the x - and y - ax e s and the 1 g measureme nt on the z - axis, respectively. the values measured for x 0 g and y 0 g correspond to the x - and y - axis offset s , and compensatio n is performed by subtracting th e se values from the output of the accelerometer to obtain the actual acceleration , as follows : x actual = x meas ? x 0g y actual = y meas ? y 0g because the z - axis measurement is performed in a +1 g field, a no - turn or single - point calibration scheme assumes an ideal sensitivity, s z , for the z - axis. this value is subtracted from z +1 g to ob tain the z - axis offset, which is then subtracted from future measured values to obtain the actual value , as follows : z 0g = z +1g ? s z z actual = z meas ? z 0g the adxl375 can automatically compensate the output for offset by usin g the offset registers (register 0x1e, register 0x1f, and register 0x20). these registers contain an 8 - bit, twos complement value that is automatically added to all measured acceleration values ; the result is then placed into the data registers. because th e value placed in an offset register is additive, a negative value in the register eliminate s a positive offset , and a positive value in the register eliminates a negative offset. the register has a scale factor of 1.56 g /lsb. as with all registers in the adxl375 , the offset registers do not retain the value s written into them when power is removed from the part. power cycling the adxl375 returns the offset registers to their default value of 0x00. because the no - turn or single - point calibration method assumes an ideal sensitivity in the z - axis, any error in the sensitivity results in offset error. data formatting at output data rates of 3200 hz and 1600 hz when using the 3200 hz or 1600 hz output data rate , the lsb of the output data - word is always 0. when the data is right justified, the lsb corresponds to bit d0 of the datax0 register ; when the data is left justified , the lsb correspon ds to bit d3 of the datax0 register.
data sheet adxl375 rev. 0 | page 29 of 32 using self - test the self - test change is defined as the difference between the acceleration output of an axis with self - test enabled and the acceleration output of the same axis with self - test disabled . due to device filtering, the output reaches its final value after 4 when enabling or disabling self - test, where = 1/(data rate ) . this definition assumes that the sensor does not move between these two measurements ; if the sensor moves, a non - self - test related shi ft corrupts the test. proper configuration of the adxl375 is necessary for an accurate self - test measurement. to configure the part for self - test, follow this procedure. 1. set the data rate from 100 hz to 800 hz, or set the data rate to 3200 hz by w rit ing to the rate bits (bits[d3:d0]) in the b w_rate register (address 0x2c). write a value from 0x0a to 0x0d, or write 0x0f to the b w_rate register . 2. f or accurate self - test measurements , configure t he par t for normal power operation by clearing the low_power bit (bit d4) in the bw_rate register (address 0x2c ). 3. after the part is configured for accurate self - test measure - ment, retrieve samples of x - , y - , and z - axis acceleration data from th e sensor and avera ge them together. the number of samples averaged is selected by the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 hz or greater that is, 10 samples at the 100 hz data rate. 4. store t he averaged values and la bel them appropriately as the value s with self - test disabled, that is, xst_off, yst_off, and zst_off. 5. enable self - test by sett ing the self_test bit (bit d7 ) in the data_format register (address 0x31). the output requires some time (a pproximately four sam ples) to settle after self - test is enabled. 6. after allowing the output to settle, retrieve samples of x - , y - , and z - axis acceleration data and average them together . it is recommended that the same number of samples be taken for th e self - test average as was done for the non - self - test average . 7. store the averaged values and label them appropriately as the value s with self - test enabled, that is, xst_on, yst_on, and zst_on. 8. disable s elf - test by clearing the self_test bit (bit d7 ) in the data_format register (a ddress 0x31). with the stored values for self - test enabled and disabled, the self - test change is as follows: x st = x s t_on ? x s t_off y st = y s t_on ? y s t_off z st = z s t_on ? z s t_off because the measured output for each axis is expressed in lsbs, x st , y st , and z st are also expressed in lsbs. these values can be converted to acceleration ( g ) by multiplying each value by the 49 m g / lsb scale factor. if the self - test change is within the valid range, the test is considered successful. generally, a part is considered to pass if the minimum magnitude of change is achieved. however, a part that changes by more than the maximum magnitude is not necessarily a failure. the self - test response in the x - and y - axes exhibit s bimodal behavior and , therefore , is not always a reliable indicator of sensor health or potential shift in device sensitivity . for this reason , perform the self - test check i n the z - axis. another effective method for using the self - test to verify accel - erometer functionality is to toggle the self - test at a certain rate and then perform an fft on the output. the fft should have a corresponding tone at the frequency where the s elf - test was toggled. using an fft in this way removes the dependency of the test on supply voltage and self - test magnitude, which can vary within a rather wide range.
adxl375 data sheet rev. 0 | page 30 of 32 axes of acceleration sensitivity a z a y a x 11669-021 figure 36 . axes of ac celeration sensitivity (corresponding output voltage increases when accelerated along the sensitive axis) 11669-022 gravity x out = 1 g y out = 0 g z out = 0 g top x out = ?1 g y out = 0 g z out = 0 g top x out = 0 g y out = 1 g z out = 0 g top x out = 0 g y out = ?1 g z out = 0 g top x out = 0 g y out = 0 g z out = 1 g x out = 0 g y out = 0 g z out = ?1 g figure 37 . output response vs. orientation to gravity
data sheet adxl375 rev. 0 | page 31 of 32 layout and design re commendations figure 38 shows the recommended printed wiring board land pattern. 3.3400 0.5500 0.2500 3.0500 0.2500 1.1450 5.3400 1.0500 1 1669- 014 figure 38 . recommended printed wiring board land pattern (dimensions shown in millimeters) package information figure 39 and table 19 provide information about the package branding for the adxl375 . 1 1669-102 3 7 5 b # y w w v v v v c n t y figure 39 . product in formation on package (top view) table 19 . package branding information branding key field description 375b part identifier for the adxl375 # rohs - compliant designation yww date code vvvv factory lot code cnty country of origin
adxl375 data sheet rev. 0 | page 32 of 32 outline dimensions b o t t o m v i e w t o p v i e w e n d v i e w s e a t i n g p l a n e 1 . 0 0 0 . 9 5 0 . 8 5 5 . 0 0 b s c 3 . 0 0 b s c p a d a 1 c o r n e r 0 . 7 9 0 . 7 4 0 . 6 9 1 6 7 8 1 4 1 3 0 . 8 0 b s c 1 . 0 1 1 . 5 0 0 . 4 9 0 . 5 0 0 . 4 9 0 . 8 1 3 0 . 5 0 0 3 - 1 6 - 2 0 1 0 - a figure 40 . 14 - terminal land grid array [lga] (cc - 14 - 1) dimensions shown in millimeters ordering guide model 1 temperature range measurement range ( g ) specified voltage (v) package description package optio n adxl375bccz ?40c to +85c 200 2.5 14- terminal land grid array [lga] cc -14-1 adxl375bccz -rl ?40c to +85c 200 2.5 14- terminal land grid array [lga] cc -14-1 adxl375bccz - rl7 ?40c to +85c 200 2.5 14- terminal land grid array [lga] cc -14-1 eval - adxl375z ?40c to + 85c evaluation board eval - adxl375z -m inertial sensor evaluation system, includes adxl375 satellite eval - adxl375z -s adxl375 satellite , standalone (can be used with other inertial sensor evaluation systems) 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their res pective owners. d11669 - 0- 8/13(0)

▲Up To Search▲

Price & Availability of ADXL375BCCZ-RL7

	To Download ADXL375BCCZ-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .